On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

This paper first explores the effects of faults on circuits implemented with controllable-polarity transistors. We propose a new fault model that suits the characteristics of these devices, and report the results of a SPICE-based analysis of the effects of faults on the behavior of some basic gates implemented with them. Hence, we show that the considered devices are able to intrinsically tolerate a rather high number of faults. We finally exploit this property to build a robust and scalable adder whose area, performance and leakage power characteristics are improved by 15%, 18% and 12%, respectively, when compared to an equivalent FinFET solution at 22-nm technology node.


Published in:
Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 491-496
Presented at:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Montpellier, France, July 8-10, 2015
Year:
2015
Publisher:
IEEE
ISBN:
978-1-4799-8718-4
Keywords:
Laboratories:




 Record created 2015-07-27, last modified 2018-09-13

n/a:
Download fulltext
PDF

Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)