In this paper, we present an improved design flow for nanoelectromechanical (NEM) relay-based combinational logic circuits. Six-terminal NEM relays can be programmed to act as 2-to-1 multiplexers. We can therefore use NEM relays to implement arbitrary combinational logic circuits. Previously, traditional logic synthesis techniques based on Binary Decision Diagrams (BDDs) have been used to map arbitrary logic functions to NEM relays. We improve this approach by showing how six-terminal relays can also be viewed as 2-to-1 multiplexers fed by comparators. This allows us to create a mapping from Biconditional BDDs (BBDDs) to NEM relays. We then show how it is possible to improve the BDD-based design flow, by presenting a methodology based on BBDD logic synthesis techniques. Experimental results show that our BBDD-based design flow reduces the average number of relays by 24% and the average critical path length by 12%. Considering an 8x8 array multiplier with different mechanical delay implementations, we show a 33% average relay count reduction.