000206784 001__ 206784
000206784 005__ 20190317000131.0
000206784 020__ $$a978-1-4799-8332-2
000206784 0247_ $$2doi$$a10.1109/LASCAS.2015.7250433
000206784 037__ $$aCONF
000206784 245__ $$aA Study on Buffer Distribution for RRAM-based FPGA Routing Structures
000206784 269__ $$a2015
000206784 260__ $$bIEEE$$c2015
000206784 336__ $$aConference Papers
000206784 520__ $$aCompared to <em>Application-Specific Integrated Circuits</em> (ASICs), <em>Field Programmable Gate Arrays</em> (FPGAs) provide reconfigurablity at the cost of lower performance and higher power consumption. Exploiting a large number of programmable switches, routing structures are mainly responsible for the performance limitation. Hence, employing more efficient switches can drastically improve the performance and reduce the power consumption of the FPGA. <em>Resistive Random Access Memory</em> (RRAM)-based switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. The lower <em>RC</em> delay of RRAM-based routing multiplexers, as compared to CMOS-based routing structures encourages us to reconsider the buffer distribution in FPGAs. This paper proposes an approach to reduce the number of buffers in the routing path of RRAM-based FPGAs. Our architectural simulations show that the use of RRAM switches improves the critical path delay by 56% as compared to CMOS switches in standard FPGA circuits at 45-nm technology node while, at the same time, the area and power are reduced, respectively, by 17% and 9%. By adapting the buffering scheme, an extra bonus of 9% for delay reduction, 5% for power reduction and 16% for area reduction can be obtained, as compared to the conventional buffering approach for RRAM-based FPGAs.
000206784 700__ $$0244625$$g197941$$aRahimian Omam, Somayyeh
000206784 700__ $$0247487$$g214644$$aTang, Xifan
000206784 700__ $$aGaillardon, Pierre-Emmanuel
000206784 700__ $$0240269$$g167918$$aDe Micheli, Giovanni
000206784 7112_ $$dFebruary 24-27, 2015$$cMontevideo, Uruguay$$a6th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2015)
000206784 773__ $$tProceedings of the 6th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2015)$$q1-4
000206784 8564_ $$uhttps://infoscience.epfl.ch/record/206784/files/SRO_LASCAS15.pdf$$zn/a$$s1103972$$yn/a
000206784 909C0 $$xU11140$$0252283$$pLSI1
000206784 909CO $$pIC$$qGLOBAL_SET$$ooai:infoscience.tind.io:206784$$pconf$$pSTI
000206784 917Z8 $$x112915
000206784 917Z8 $$x112915
000206784 917Z8 $$x112915
000206784 937__ $$aEPFL-CONF-206784
000206784 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000206784 980__ $$aCONF