A Study on Buffer Distribution for RRAM-based FPGA Routing Structures

Compared to <em>Application-Specific Integrated Circuits</em> (ASICs), <em>Field Programmable Gate Arrays</em> (FPGAs) provide reconfigurablity at the cost of lower performance and higher power consumption. Exploiting a large number of programmable switches, routing structures are mainly responsible for the performance limitation. Hence, employing more efficient switches can drastically improve the performance and reduce the power consumption of the FPGA. <em>Resistive Random Access Memory</em> (RRAM)-based switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. The lower <em>RC</em> delay of RRAM-based routing multiplexers, as compared to CMOS-based routing structures encourages us to reconsider the buffer distribution in FPGAs. This paper proposes an approach to reduce the number of buffers in the routing path of RRAM-based FPGAs. Our architectural simulations show that the use of RRAM switches improves the critical path delay by 56% as compared to CMOS switches in standard FPGA circuits at 45-nm technology node while, at the same time, the area and power are reduced, respectively, by 17% and 9%. By adapting the buffering scheme, an extra bonus of 9% for delay reduction, 5% for power reduction and 16% for area reduction can be obtained, as compared to the conventional buffering approach for RRAM-based FPGAs.

Published in:
Proceedings of the 6th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2015), 1-4
Presented at:
6th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2015), Montevideo, Uruguay, February 24-27, 2015

 Record created 2015-03-18, last modified 2019-03-17

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