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A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS
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A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with[...]
-
Cevrero, Alessandro
et al
additional
file(s):
VLSI15_1
version 1
VLSI15_1.pdf
[1.94 MB]
27 Jan 2018, 12:50