000206303 001__ 206303
000206303 005__ 20181116143623.0
000206303 037__ $$aCONF
000206303 245__ $$aA 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS
000206303 269__ $$a2015
000206303 260__ $$c2015
000206303 336__ $$aConference Papers
000206303 520__ $$aThis work reports an 8-lane single-ended RX featuring compact and low power far-end crosstalk (FEXT) cancellation circuits. The RX data-path consists of a cross continuous-time linear equalizer (XCTLE) to remove FEXT by nearest aggressors within the channel bundle. Residual post-cursor FEXT is suppressed by a direct feedback 7x8-tap cross decision feedback equalizer (XDFE). A CTLE and 8-tap DFE equalize single-ended channels with 28dB insertion loss at Nyquist frequency without TX FFE. The circuit, fabricated in 32nm SOI CMOS, was measured to receive 7Gb/s/pin PRBS11 data at BER< 10^-12 with 12.5%UI margin. It occupies 300x350um2 with an energy efficiency of 5.9mW/Gb/s.
000206303 700__ $$0242449$$aCevrero, Alessandro$$g176546
000206303 700__ $$0243957$$aAprile, Cosimo$$g199128
000206303 700__ $$aFrancese, Pier Andrea
000206303 700__ $$aBapst, Urs
000206303 700__ $$aMenolfi, Christian
000206303 700__ $$aBraendli, Matthias
000206303 700__ $$aKossel, Marcel
000206303 700__ $$aMorf, Thomas
000206303 700__ $$0242446$$aKull, Lukas$$g197929
000206303 700__ $$aYueksel, Hazar
000206303 700__ $$0251463$$aÖzkaya, Ilter$$g251913
000206303 700__ $$0240162$$aLeblebici, Yusuf$$g112194
000206303 700__ $$0243957$$aCevher, Volkan$$g199128
000206303 700__ $$aToifl, Thomas
000206303 7112_ $$aSymposium on VLSI Circuits$$cKyoto, Japan$$dJune 15-19, 2015
000206303 8564_ $$s2034029$$uhttps://infoscience.epfl.ch/record/206303/files/VLSI15_1.pdf
000206303 909C0 $$0252051$$pLSM$$xU10325
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000206303 937__ $$aEPFL-CONF-206303
000206303 973__ $$aEPFL$$rREVIEWED$$sACCEPTED
000206303 980__ $$aCONF