A 4x9 Gb/s 1 pJ/b NRZ/Multi-Tone Serial-Data Transceiver with Crosstalk Reduction Architecture for Multi-Drop Memory Interfaces in 40nm CMOS
Gharibdoust, Kiarash; Tajalli, Seyed Armin; Leblebici, Yusuf
2015

Abstract

An aggregated 36 Gb/s low power 4-lanes mixed NRZ/multi-tone transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40nm CMOS technology. The proposed architecture achieves 1 pJ/bit power efficiency in the entire link (TX + RX) for an MDB channel with 45 dB loss at 3 GHz. The multi-tone nature of the proposed transceiver is employed to properly reduce crosstalk (Xtalk) induced noise and to improve overall power efficiency. © 2015 JSAP.

Details

Title A 4x9 Gb/s 1 pJ/b NRZ/Multi-Tone Serial-Data Transceiver with Crosstalk Reduction Architecture for Multi-Drop Memory Interfaces in 40nm CMOS
Author(s) Gharibdoust, Kiarash ; Tajalli, Seyed Armin ; Leblebici, Yusuf
Published in 2015 Symposium on VLSI Circuits (VLSI Circuits)
Pages C180-C181
Conference 2015 Symposium on VLSI Circuits, Kyoto, Japan, June 15-19, 2015
Date 2015
ISBN 978-4-86348-502-0
DOI https://doi.org/10.1109/VLSIC.2015.7231253
Additional link URL
Laboratories LSM
Record Appears in Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > LSM - Microelectronic Systems Laboratory
Conference Papers
Work produced at EPFL
Published
Record creation date 2015-03-11

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