A 4x9 Gb/s 1 pJ/b NRZ/Multi-Tone Serial-Data Transceiver with Crosstalk Reduction Architecture for Multi-Drop Memory Interfaces in 40nm CMOS

An aggregated 36 Gb/s low power 4-lanes mixed NRZ/multi-tone transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40nm CMOS technology. The proposed architecture achieves 1 pJ/bit power efficiency in the entire link (TX + RX) for an MDB channel with 45 dB loss at 3 GHz. The multi-tone nature of the proposed transceiver is employed to properly reduce crosstalk (Xtalk) induced noise and to improve overall power efficiency. © 2015 JSAP.


Published in:
2015 Symposium on VLSI Circuits (VLSI Circuits), C180-C181
Presented at:
2015 Symposium on VLSI Circuits, Kyoto, Japan, June 15-19, 2015
Year:
2015
ISBN:
978-4-86348-502-0
Laboratories:




 Record created 2015-03-11, last modified 2018-09-13

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