A 2.4 GHz low power polar transmitter is proposed in this paper. A dynamic biasing circuit, controlled by a digital envelope signal, is used as a direct digital-to-RF envelope converter. It effectively linearizes the input-output characteristic of the overdriven cascode class-C power amplifier used as the output stage, by dynamically adjusting the bias voltage of the cascode transistor. An equivalent baseband model of the transmitter is presented and used to optimize system parameters and give initial assessment of the achievable performance in terms of efficiency and linearity. Based on these simulations, parameters for transistor-level implementation of the bias circuit are derived. The transmitter is designed in a 65 nm CMOS technology. The post layout simulations indicate that the transmitter successfully meets the requirements of the IEEE 802.15.6 standard for wireless body area networks. The simulated amplifier consumes 4.75 mA from a 1.2 V supply while delivering 1.45 dBm of output power with a peak efficiency of 24 %. The entire transmitter, including the PLL, consumes 7.5 mA.