Low-Voltage Read/Write Circuit Design for Transistorless ReRAM Crossbar Arrays in 180nm CMOS Technology
This paper presents a read-write design solution for passive ReRAM crossbar memory arrays to overcome the sneak current paths problem. The proposed circuitry includes an auto-calibration feature to overcome the sneak current effects during the READ operation, and a WRITE protocol to minimize the current at each row and column lines. The presented circuit has been designed in 180 nm standard CMOS technology based on the electrical characteristics of fabricated ReRAM devices.
Record created on 2015-01-22, modified on 2016-08-09