000204266 001__ 204266
000204266 005__ 20190317000056.0
000204266 020__ $$a978-3-9815-3704-8
000204266 037__ $$aCONF
000204266 245__ $$aTackling the Bottleneck of Delay Tables in 3D Ultrasound Imaging
000204266 269__ $$a2015
000204266 260__ $$bIEEE$$c2015
000204266 336__ $$aConference Papers
000204266 520__ $$a3D ultrasound imaging is quickly becoming a refer- ence technique for high-quality, accurate, expressive diagnostic medical imaging. Unfortunately, its computation requirements are huge and, today, demand expensive, power-hungry, bulky processing resources. A key bottleneck is the receive beamforming operation, which requires the application of many permutations of fine-grained delays among the digitized received echoes. To apply these delays in the digital domain, in principle large tables (billions of coefficients) are needed, and the access bandwidth to these tables can reach multiple TB/s, meaning that their storage both on-chip and off-chip is impractical. However, smarter implementations of the delay generation function, including forgoing the tables altogether, are possible. In this paper we explore efficient strategies to compute the delay function that controls the reconstruction of the image, and present a feasibility analysis for an FPGA platform.
000204266 700__ $$aIbrahim, Aya
000204266 700__ $$aHager, Pascal
000204266 700__ $$0241996$$g169841$$aAngiolini, Federico
000204266 700__ $$aArditi, Marcel
000204266 700__ $$0243773$$g171049$$aBenini, Luca
000204266 700__ $$aDe Micheli, Giovanni$$g167918$$0240269
000204266 7112_ $$dMarch 9-13, 2015$$cGrenoble, France$$a2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)
000204266 773__ $$tProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)$$q1683-1688
000204266 8564_ $$uhttps://infoscience.epfl.ch/record/204266/files/1151.pdf$$zn/a$$s268108$$yn/a
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000204266 937__ $$aEPFL-CONF-204266
000204266 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000204266 980__ $$aCONF