1T Capacitor-less DRAM cell based on asymmetric Tunnel FET design
In this work we propose and demonstrate the use of a Tunnel FET (TFET) as capacitorless DRAM cell based on TCAD simulations and experiments. We report more experimental results on Tunnel FETs implemented as a double-gate (DG) fully-depleted Silicon-On-Insulator (FD-SOI) devices. The Tunnel FET based DRAM cell has an asymmetric body and a partial overlap of the top gate (LG1) with a total overlap of the back gate over the channel region (LG2). A potential well is created by biasing the back gate (VG2) in accumulation while the front gate (VG1) is in inversion. Holes from the p+ source are injected by the forward-bias p+i junction and stored in the electrically induced potential well. Programming conditions and related transients are reported and the role of temperature is investigated.
- URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6990484&sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A6423298%29
Record created on 2015-01-07, modified on 2016-08-09