A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations

Minimizing buffer sizes of dynamic dataflow implementations without introducing deadlocks or reducing the design performance is in general an important and useful design objective. Indeed, buffer sizes that are too small causing a system to deadlock during execution, or dimensioning unnecessarily large sizes leading to a resource inefficient design are both not a desired design option. This paper presents an implementation, validation, and comparison of several buffer size optimization techniques for the generic class of dynamic dataflow model of computation called the dataflow process network. The paper presents an heuristic capable of finding a close-to-minimum buffer size configuration for deadlock-free executions, and a methodology to efficiently explore different configurations for feasible design alternatives. The approach is demonstrated using as experimental design case, an MPEG-4 AVC/H.264 decoder implemented on an FPGA.


Published in:
2014 Ieee International Conference On Acoustics, Speech And Signal Processing (Icassp)
Presented at:
IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014
Year:
2014
Publisher:
New York, Ieee
ISSN:
1520-6149
ISBN:
978-1-4799-2893-4
Keywords:
Laboratories:




 Record created 2014-12-30, last modified 2018-09-13


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