Dynamic stability and noise margins of SRAM arrays in nanoscaled technologies
SRAM stability is one of the primary bottlenecks of current VLSI system design, and the unequivocal supply voltage scaling limiter. Static noise margin metrics have long been the de-facto standard for measuring this stability and estimating the yield of SRAM arrays. However, in modern process technologies, under scaled supply voltages and increased process variations, these traditional metrics are no longer sufficient. Recent research has analyzed the dynamic behavior and stability of SRAM circuits, leading to dynamic stability metrics and dynamic noise margin definition. This paper provides a brief overview of the limitations of static noise margin metrics and the resulting dynamic stability and noise margin concepts that have been proposed to overcome them.
Keywords: SRAM chips ; VLSI ; circuit stability ; integrated circuit noise ; limiters ; nanoelectronics ; SRAM arrays ; SRAM circuit stability ; VLSI system design ; dynamic noise margin ; dynamic stability ; dynamic stability metrics ; nanoscaled technology ; noise margins ; process variations ; static noise margin metrics ; unequivocal supply voltage scaling limiter ; Europe ; Wireless sensor networks ; Dynamic Noise Margin ; Phase Portrait ; SRAM ; Separatrix ; Stability Analysis ; Static Noise Margin
Record created on 2014-11-12, modified on 2016-08-09