4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes
Gain-Cell embedded DRAM (GC-eDRAM) has recently been recognized as a possible alternative to traditional SRAM. While GC-eDRAM inherently provides high-density, low-leakage, low-voltage, and 2-ported operation, its limited retention time requires periodic, power-hungry refresh cycles. This drawback is further enhanced at scaled technologies, where increased subthreshold leakage currents and decreased in-cell storage capacitances result in faster data deterioration. In this paper, we present a novel 4T GC-eDRAM bitcell that utilizes an internal feedback mechanism to significantly increase the data retention time in scaled CMOS technologies. A 2 kb memory macro was implemented in a low-power 65nm CMOS technology, displaying an over 3× improvement in retention time over the best previous publication at this node. The resulting array displays a nearly 5× reduction in retention power (despite the refresh power component) with a 40% reduction in bitcell area, as compared to a standard 6T SRAM.
Keywords: CMOS memory circuits ; DRAM chips ; circuit feedback ; leakage currents ; low-power electronics ; 4T GC-eDRAM bitcell ; 4T gain-cell ; bitcell area reduction ; decreased in-cell storage capacitances ; gain-cell embedded DRAM ; internal feedback mechanism ; low-power CMOS technology ; memory macro ; periodic power-hungry refresh cycles ; scaled CMOS nodes ; size 65 nm ; standard 6T SRAM ; storage capacity 2 Kbit ; subthreshold leakage currents ; ultra-low retention power ; CMOS integrated circuits ; Computer architecture ; Leakage currents ; Microprocessors ; Random access memory
Record created on 2014-11-12, modified on 2016-08-09