4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes

Gain-Cell embedded DRAM (GC-eDRAM) has recently been recognized as a possible alternative to traditional SRAM. While GC-eDRAM inherently provides high-density, low-leakage, low-voltage, and 2-ported operation, its limited retention time requires periodic, power-hungry refresh cycles. This drawback is further enhanced at scaled technologies, where increased subthreshold leakage currents and decreased in-cell storage capacitances result in faster data deterioration. In this paper, we present a novel 4T GC-eDRAM bitcell that utilizes an internal feedback mechanism to significantly increase the data retention time in scaled CMOS technologies. A 2 kb memory macro was implemented in a low-power 65nm CMOS technology, displaying an over 3× improvement in retention time over the best previous publication at this node. The resulting array displays a nearly 5× reduction in retention power (despite the refresh power component) with a 40% reduction in bitcell area, as compared to a standard 6T SRAM.

Published in:
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2177-2180
Presented at:
2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, Australia, 1-5 June 2014

 Record created 2014-11-12, last modified 2018-01-28

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