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As memory density continues to grow in modern systems, accurate analysis of SRAM stability is increasingly important to ensure high yields. Traditional static noise margin metrics fail to capture the dynamic characteristics of SRAM behavior, leading to expensive over-design and disastrous under-design. One of the central components of more accurate dynamic stability analysis is the separatrix; however, its straightforward extraction is extremely time-consuming, and efficient methods are either non-accurate or extremely difficult to implement. In this paper, we propose a novel algorithm for fast separatrix tracing of any given SRAM topology, designed with industry standard transistor models in nano-scaled technologies. The proposed algorithm is applied to both standard 6T SRAM bitcells, as well as previously proposed alternative sub-threshold bitcells, providing up to three orders-of-magnitude speedup, as compared to brute force methods. In addition, for the first time, statistical Monte Carlo separatrix distributions are plotted.