Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and low yield). In this paper, we propose a new TSV sharing method for a circuit-switched 3-D mesh-of-tree (MoT) interconnect, which supports high-throughput and low-latency communication between processing cores and 3-D stacked multibanked L2 scratchpad memory. The proposed method supports traffic balancing and TSV-failure tolerant routing. The proposed method advocates a modular design strategy to allow stacking multiple identical memory dies without the need for different masks for dies at different levels in the memory stack. We also investigate various parameters of 3-D memory stacking (e.g., fabrication technology, TSV bonding technique, number of memory tiers, and TSV sharing scheme) that affect interconnect latency, system performance, and fabrication cost. Compared to conventional MoT interconnect that is straightforwardly adapted to 3-D integration, the proposed method yields up to (times 2.11) and (times 1.11) improvements in terms of cost efficiency (i.e., performance/cost) for microbump TSV bonding and direct Cu–Cu TSV bonding techniques, respectively.

Published in:
IEEE Transactions on Very Large Scale Integration Systems, 23, 9, 1828-1841
Piscataway, Institute of Electrical and Electronics Engineers

 Record created 2014-10-09, last modified 2019-03-17

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