A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

An area- and power-optimized asynchronous 32x interleaved SAR ADC achieving 36 GS/s at 110mW and 1V supply on the interleaver and 0.9V on the SAR ADCs is presented. The ADC features a 2-channel interleaver with data demultiplexing for enhanced bandwidth, a power- and area optimized binary SAR ADC, and an area optimized clocked reference buffer with a tunable constant current source. It achieves 32.6 dB SNDR up to 3GHz and 31.6 dB up to 18 GHz input frequency and 98 fJ/conversion-step with a core chip area of 340x140 um2 in 32nm SOI CMOS technology.

Published in:
Proceedings of the 2014 IEEE Asian Solid-State Circuits Conference
Presented at:
2014 IEEE Asian Solid-State Circuits Conference, Kaohsiung, Taiwan, 10-12 November, 2014

 Record created 2014-10-08, last modified 2018-03-17

Rate this document:

Rate this document:
(Not yet reviewed)