000201962 001__ 201962
000201962 005__ 20190331192701.0
000201962 0247_ $$2doi$$a10.1109/Tnano.2014.2363386
000201962 022__ $$a1536-125X
000201962 02470 $$2ISI$$a000345087900003
000201962 037__ $$aARTICLE
000201962 245__ $$aTop-Down Fabrication of Gate-All-Around Vertically-Stacked Silicon Nanowire FETs with Controllable Polarity
000201962 269__ $$a2014
000201962 260__ $$bInstitute of Electrical and Electronics Engineers$$c2014$$aPiscataway
000201962 300__ $$a10
000201962 336__ $$aJournal Articles
000201962 520__ $$aAsthe currentMOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the fabrication of novel ambipolar Silicon nanowire (SiNW) Schottky-barrier (SB) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. A top-down approach was employed for the nanowire fabrication, using an e-beam lithography defined design pattern. In these transistors, one gate electrode enables the dynamic configuration of the device polarity (n- or p-type) by electrostatic doping of the channel in proximity of the source and drain SBs. The other gate electrode, acting on the center region of the channel switches ON or OFF the device. Measurement results on silicon show I-on/I-off > 10(6) and subthreshold slopes approaching the thermal limit, SS approximate to 64 mV/dec (70 mV/dec) for p(n)-type operation in the same physical device. Finally, we show that the XOR logic operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional two-transistor XOR gate.
000201962 6531_ $$aAmbipolar transistor
000201962 6531_ $$aBosch process
000201962 6531_ $$adouble-gate
000201962 6531_ $$adual-gate
000201962 6531_ $$ae-beam lithography
000201962 6531_ $$agate-all-around (GAA)
000201962 6531_ $$apolarity control
000201962 6531_ $$asilicon nanowire (SiNW)
000201962 6531_ $$atop-down fabrication
000201962 6531_ $$aXOR logic gate
000201962 700__ $$0244574$$g181371$$aDe Marchi, Michele
000201962 700__ $$0242417$$g181895$$aSacchetto, Davide
000201962 700__ $$0245831$$g212096$$aZhang, Jian
000201962 700__ $$aFrache, Stefano
000201962 700__ $$aGaillardon, Pierre-Emmanuel
000201962 700__ $$aLeblebici, Yusuf$$g112194$$0240162
000201962 700__ $$aDe Micheli, Giovanni$$g167918$$0240269
000201962 773__ $$j13$$tIEEE Transactions on Nanotechnology$$k6$$q1029-1038
000201962 8564_ $$uhttps://infoscience.epfl.ch/record/201962/files/06923475.pdf$$zn/a$$s1624778$$yn/a
000201962 909C0 $$xU10325$$0252051$$pLSM
000201962 909C0 $$0252283$$pLSI1$$xU11140
000201962 909CO $$qGLOBAL_SET$$pSTI$$pIC$$particle$$ooai:infoscience.tind.io:201962
000201962 917Z8 $$x112915
000201962 917Z8 $$x112915
000201962 917Z8 $$x112915
000201962 917Z8 $$x112194
000201962 917Z8 $$x112915
000201962 937__ $$aEPFL-ARTICLE-201962
000201962 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000201962 980__ $$aARTICLE