Fast Process Variation Analysis in Nano-Scaled Technologies Using Column-Wise Sparse Parameter Selection

With growing concern about process variation in deeply nano-scaled technologies, parameterized device and circuit modeling is becoming very important for design and verification. However, the high dimensionality of parameter space is a serious modeling challenge for emerging VLSI technologies, where the models are increasingly more complex. In this paper, we propose and validate a feature selection method to reduce the circuit modeling complexity associated with high parameter dimensionality. Despite the commonly used methods such as <i>Principal Component Analysis</i> (PCA) and <i>Independent Component Analysis</i> (ICA), this method is capable of dealing with mixed Gaussian and non-Gaussian parameters, and performs a parameter selection in the input space rather than creating a new space. By considering non-linear dependencies among input parameters and outputs, the method results in an effective parameter selection. The application of this method is demonstrated in digital circuit timing analysis to effectively reduce the number of simulations. The experimental results on <i>Double-Gate Silicon NanoWire FET</i> (DG-SiNWFET) technology indicate 2.5× speed up in timing variation analysis of the ISCAS89-s27 benchmark with a controlled average error bound of 9.4%.

Published in:
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), 163-168
Presented at:
IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), Paris, France, July 8-10, 2014

 Record created 2014-09-30, last modified 2018-03-17

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