TSPC Flip-Flop Circuit Design with Three-Independent-Gate Silicon Nanowire FETs

True Single-Phase Clock (TSPC) Flip-Flops, based on dynamic logic implementation, are area-saving and high-speed compared to standard static flip-flops. Furthermore, logic gates can be embedded into TSPC flip-flops which significantly improves performance. As a promising approach to keep the pace of Moore's Law, functionality-enhanced devices with multiple independent gates have drown many recent interests. In particular, Three-Independent-Gate Silicon Nanowire FETs (TIG SiNWFETs) can realize the functionality of two serial transistors in a single device. Therefore, they open new opportunities to compact designs in both arithmetic and control circuits. In this paper, we propose TSPC flip-flop implementation with asynchronous set and reset using the compactness of TIG SiNWFET. Electrical simulations show that TIG SiNWFET-based TSPC flip-flop improves nearly 20%, 30% and 7% in area, delay and leakage power respectively as compared to its LSTP FinFET counterpart at 22nm.


Publié dans:
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 1660-1663
Présenté à:
IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Austrailia, June 1-5, 2014
Année
2014
Publisher:
IEEE
ISBN:
978-1-4799-3431-7
Mots-clefs:
Laboratoires:




 Notice créée le 2014-09-30, modifiée le 2019-03-17

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