000201909 001__ 201909
000201909 005__ 20190317000012.0
000201909 0247_ $$2doi$$a10.1109/FPL.2014.6927429
000201909 037__ $$aCONF
000201909 245__ $$aPattern-Based FPGA Logic Block and Clustering Algorithm
000201909 269__ $$a2014
000201909 260__ $$bIEEE$$c2014
000201909 336__ $$aConference Papers
000201909 520__ $$aIn classical FPGA, LUTs and DFFs are pre-packed into BLEs and then BLEs are grouped into logic blocks. We propose a novel logic block architecture with fast combinational paths between LUTs, called pattern-based logic blocks. A new clustering algorithm is developed to release the potential of pattern-based logic blocks. Experimental results show that the novel architecture and the associated clustering algorithm lead to a 14% performance gain and a 8% wirelength reduction with a 3% area overhead compared to conventional architecture in large control-instensive benchmarks.
000201909 700__ $$0247487$$g214644$$aTang, Xifan
000201909 700__ $$aGaillardon, Pierre-Emmanuel
000201909 700__ $$aDe Micheli, Giovanni$$g167918$$0240269
000201909 7112_ $$dSeptember 2-4, 2014$$cMunich, Germany$$a24th International Conference on Field Programmable Logic and Applications (FPL)
000201909 773__ $$tProceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL)$$q1-4
000201909 8564_ $$uhttps://infoscience.epfl.ch/record/201909/files/fpl14_final.pdf$$zn/a$$s365890$$yn/a
000201909 909C0 $$xU11140$$0252283$$pLSI1
000201909 909CO $$pIC$$ooai:infoscience.tind.io:201909$$qGLOBAL_SET$$pconf$$pSTI
000201909 917Z8 $$x112915
000201909 917Z8 $$x112915
000201909 917Z8 $$x112915
000201909 937__ $$aEPFL-CONF-201909
000201909 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000201909 980__ $$aCONF