Pattern-Based FPGA Logic Block and Clustering Algorithm

In classical FPGA, LUTs and DFFs are pre-packed into BLEs and then BLEs are grouped into logic blocks. We propose a novel logic block architecture with fast combinational paths between LUTs, called pattern-based logic blocks. A new clustering algorithm is developed to release the potential of pattern-based logic blocks. Experimental results show that the novel architecture and the associated clustering algorithm lead to a 14% performance gain and a 8% wirelength reduction with a 3% area overhead compared to conventional architecture in large control-instensive benchmarks.


Published in:
Proceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL), 1-4
Presented at:
24th International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, September 2-4, 2014
Year:
2014
Publisher:
IEEE
Laboratories:




 Record created 2014-09-30, last modified 2018-09-13

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