000201876 001__ 201876
000201876 005__ 20190331192700.0
000201876 0247_ $$2doi$$a10.1109/Ted.2014.2359112
000201876 022__ $$a0018-9383
000201876 02470 $$2ISI$$a000344544200012
000201876 037__ $$aARTICLE
000201876 245__ $$aPolarity-Controllable Silicon Nanowire Transistors with Dual Threshold Voltages
000201876 269__ $$a2014
000201876 260__ $$bInstitute of Electrical and Electronics Engineers$$c2014$$aPiscataway
000201876 300__ $$a7
000201876 336__ $$aJournal Articles
000201876 520__ $$aGate-all-around (GAA) silicon nanowires enable an unprecedented electrostatic control on the semiconductor channel that can push device performance with continuous scaling. In modern electronic circuits, the control of the threshold voltage is essential for improving circuit performance and reducing static power consumption. Here, we propose a silicon Wnanowire transistor with three independent GAA electrodes, demonstrating, within a unique device, a dynamic configurability in terms of both polarity and threshold voltage (V-T). This silicon nanowire transistor is fabricated using a vertically stacked structure with a top-down approach. Unlike conventional threshold voltage modulation techniques, the threshold control of this device is achieved by adapting the control scheme of the potential barriers at the source and drain interfaces and in the channel. Compared to conventional dual-threshold techniques, the proposed device does not tradeoff the leakage reduction at the detriment of the ON-state current, but only through a later turn-ON coming from a higher V-T. This property offers leakage control at a reduction of loss in performance. The measured characteristic demonstrates a threshold voltage difference of similar to 0.5 V between low-V-T and high-V-T configurations, while high-V-T configuration reduces the leakage current by two orders of magnitude as compared to low-V-T configuration.
000201876 6531_ $$aPolarity
000201876 6531_ $$aSchottky barrier
000201876 6531_ $$asilicon nanowire
000201876 6531_ $$athreshold voltage
000201876 700__ $$0245831$$g212096$$aZhang, Jian
000201876 700__ $$0244574$$g181371$$aDe Marchi, Michele
000201876 700__ $$0242417$$g181895$$aSacchetto, Davide
000201876 700__ $$aGaillardon, Pierre-Emmanuel
000201876 700__ $$aLeblebici, Yusuf$$g112194$$0240162
000201876 700__ $$aDe Micheli, Giovanni$$g167918$$0240269
000201876 773__ $$j61$$tIEEE Transactions on Electron Devices$$k11$$q3654-3660
000201876 8564_ $$uhttps://infoscience.epfl.ch/record/201876/files/06915729.pdf$$zn/a$$s2236943$$yn/a
000201876 909C0 $$xU10325$$0252051$$pLSM
000201876 909C0 $$0252283$$pLSI1$$xU11140
000201876 909CO $$qGLOBAL_SET$$pSTI$$pIC$$particle$$ooai:infoscience.tind.io:201876
000201876 917Z8 $$x112915
000201876 917Z8 $$x112915
000201876 917Z8 $$x112915
000201876 917Z8 $$x112194
000201876 917Z8 $$x112915
000201876 937__ $$aEPFL-ARTICLE-201876
000201876 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000201876 980__ $$aARTICLE