Majority Logic Synthesis for Spin Wave Technology

<i>Spin Wave Devices</i> (SWDs) are promising beyond-CMOS candidates. Unlike traditional charge-based technologies, SWDs use spin as information carrier that propagates in waves. In this scenario, the logic primitive for computation is the majority gate. The majority gate has a greater expressive power than standard NAND/NOR gates, allowing SWD circuits to be more compact than CMOS, already at the logic level. Also, because there is not charge carrier transport, SWDs are estimated to have ultra-low power consumption. However, in order to exploit this opportunity, a native majority synthesis methodology is needed to fit the SWD technology needs. In this paper, we employ <i>Majority-Inverter Graphs</i> (MIGs) to naturally represent and synthesize SWD circuits. Thanks to the correspondence between the functionality of SWD primitive gates and MIG elements, MIG optimization intrinsically aims at minimum cost SWD implementations. Experimental results over MCNC benchmarks validate the efficiency of MIGs in SWD synthesis. As compared to traditional <i>AND-Inverter Graph</i> (AIG) synthesis, MIGs generate, on average, SWD circuits with 1.30× smaller <i>area-delay-power product</i> (ADP), improving their delay performance by 18%.

Published in:
Proceedings of the Euromicro Conference on Digital System Design 2014
Presented at:
Euromicro Conference on Digital System Design 2014, Verona, Italy, August 27-29, 2014

 Record created 2014-09-04, last modified 2019-03-17

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