System-level Assessment and Area Evaluation of Spin Wave Logic Circuits

Spin Wave Devices (SWDs) are promising candidates for scaling electronics beyond the domain of CMOS. In contrast to traditional charge-based technologies, SWDs rely on propagating oscillation of magnetization as information carrier. Thanks to the intrinsic wave computation capability of these devices, the majority gate is implemented with low physical re- sources. Being more expressive than standard NAND/NOR gates, the compact majority gate pushes further the expected benefits of SWDs over CMOS. In this paper, we present a realistic design framework for SWD-based logic circuits, accounting for both limitations and advantages deriving from the new technology. We use a majority logic synthesis tool to fully exploit the SWD functionality. In the experiments, we focus on the estimated area. We consider several arithmetic-intensive benchmarks, and compare their SWD area with three state-of-the-art CMOS nodes. We show that an area reduction up to 11.3× is possible, as compared to a 10nm CMOS technology.

Published in:
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2014), 25-30
Presented at:
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2014), Paris, France, July 8-10, 2014

Note: The status of this file is: EPFL only

 Record created 2014-09-04, last modified 2018-12-03

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