000200864 001__ 200864
000200864 005__ 20190509132511.0
000200864 0247_ $$2doi$$a10.5075/epfl-thesis-6278
000200864 02470 $$2urn$$aurn:nbn:ch:bel-epfl-thesis6278-1
000200864 02471 $$2nebis$$a10206547
000200864 037__ $$aTHESIS
000200864 041__ $$aeng
000200864 088__ $$a6278
000200864 245__ $$aSpeed/Power/Area Trade-offs for High Speed Inter Layer Data Transmission in 3D Stacked ICs
000200864 269__ $$a2014
000200864 260__ $$bEPFL$$c2014$$aLausanne
000200864 336__ $$aTheses
000200864 502__ $$aDr G. Boero (président) ;  Prof. Y. Leblebici, Prof. G. De Micheli (directeurs) ;  Prof. A.P. Burg,   Dr F. Clermidy,   Prof. A.K. Coskun (rapporteurs)
000200864 6531_ $$a3D ICs
000200864 6531_ $$aThrough Silicon Vias TSVs
000200864 6531_ $$aChip Multi-Processors CMPs
000200864 6531_ $$ahigh speed serial links
000200864 700__ $$0242424$$g188027$$aBeanato, Giulia
000200864 720_2 $$aLeblebici, Yusuf$$edir.$$g112194$$0240162
000200864 720_2 $$aDe Micheli, Giovanni$$edir.$$g167918$$0240269
000200864 8564_ $$uhttps://infoscience.epfl.ch/record/200864/files/EPFL_TH6278.pdf$$zn/a$$s26512535$$yn/a
000200864 909C0 $$xU10325$$0252051$$pLSM
000200864 909C0 $$xU11189$$0252284$$pLSI2
000200864 909CO $$ooai:infoscience.tind.io:200864$$qDOI2$$qGLOBAL_SET$$qIC$$pthesis$$pSTI$$pDOI
000200864 917Z8 $$x108898
000200864 917Z8 $$x108898
000200864 917Z8 $$x108898
000200864 917Z8 $$x108898
000200864 918__ $$dEDMI$$cIEL$$aSTI
000200864 919__ $$aLSM
000200864 920__ $$b2014$$a2014-8-26
000200864 970__ $$a6278/THESES
000200864 973__ $$sPUBLISHED$$aEPFL
000200864 980__ $$aTHESIS