000200864 001__ 200864
000200864 005__ 20190316235957.0
000200864 0247_ $$2doi$$a10.5075/epfl-thesis-6278
000200864 02470 $$2urn$$aurn:nbn:ch:bel-epfl-thesis6278-1
000200864 02471 $$2nebis$$a10206547
000200864 037__ $$aTHESIS
000200864 041__ $$aeng
000200864 088__ $$a6278
000200864 245__ $$aSpeed/Power/Area Trade-offs for High Speed Inter Layer Data Transmission in 3D Stacked ICs
000200864 269__ $$a2014
000200864 260__ $$aLausanne$$bEPFL$$c2014
000200864 336__ $$aTheses
000200864 502__ $$aDr G. Boero (président) ;  Prof. Y. Leblebici, Prof. G. De Micheli (directeurs) ;  Prof. A.P. Burg,   Dr F. Clermidy,   Prof. A.K. Coskun (rapporteurs)
000200864 6531_ $$a3D ICs
000200864 6531_ $$aThrough Silicon Vias TSVs
000200864 6531_ $$aChip Multi-Processors CMPs
000200864 6531_ $$ahigh speed serial links
000200864 700__ $$0242424$$aBeanato, Giulia$$g188027
000200864 720_2 $$0240162$$aLeblebici, Yusuf$$edir.$$g112194
000200864 720_2 $$0240269$$aDe Micheli, Giovanni$$edir.$$g167918
000200864 8564_ $$s26512535$$uhttps://infoscience.epfl.ch/record/200864/files/EPFL_TH6278.pdf$$yn/a$$zn/a
000200864 909C0 $$0252051$$pLSM$$xU10325
000200864 909C0 $$0252284$$pLSI2$$xU11189
000200864 909CO $$ooai:infoscience.tind.io:200864$$pthesis$$pSTI$$pDOI$$qDOI2$$qGLOBAL_SET$$qIC
000200864 917Z8 $$x108898
000200864 917Z8 $$x108898
000200864 917Z8 $$x108898
000200864 917Z8 $$x108898
000200864 918__ $$aSTI$$cIEL$$dEDMI
000200864 919__ $$aLSM
000200864 920__ $$a2014-8-26$$b2014
000200864 970__ $$a6278/THESES
000200864 973__ $$aEPFL$$sPUBLISHED
000200864 980__ $$aTHESIS