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As CMOS processes continue to scale to smaller dimensions, the increased fT of the devices and smaller parasitic capacitance allow formore power efficient and faster digital circuits to be made. But at the same time, output impedance of transistors has gone down, as have the power supply voltages, and leakage currents have increased. These changes in the technology havemade analog design more difficult.More specifically, the design of a high gain op-amp, a fundamental analog building block, has becomemore difficult in scaled processes. In this work, to improve the performance considering the speed, accuracy and power consumption of the analog-digital interface, both system level optimization and circuit level technique are explored. At first, a generalized graphic model (GGM) is proposed to analyze the resolution of ADC for wireless receiver. This model could show the trade-off between ADC the RF front-end in the power level graph. As a result, the optimization between them becomes practical. Next, two kinds of open loop ADCs are designed and implemented for ultra-wide bandwidth (UWB) receiver and capacitive sensor interface respectively. There is no closed loop stage in the flash ADC, which ensures the fastest conversion speed. An intended spatial filter technique is adopted to attenuate the distortion coming from the interpolation network. The successive approximation (SAR) ADC based switched capacitor sensor interface digitizes the capacitance variation to binary code. A cascade binary weighted DAC is used to reduce the power consumption and area. The noise and distortion performance are optimized throughout the design.