000200483 001__ 200483
000200483 005__ 20190509132510.0
000200483 0247_ $$2doi$$a10.5075/epfl-thesis-6176
000200483 02470 $$2urn$$aurn:nbn:ch:bel-epfl-thesis6176-2
000200483 02471 $$2nebis$$a10195928
000200483 037__ $$aTHESIS
000200483 041__ $$aeng
000200483 088__ $$a6176
000200483 245__ $$aDigitization Technique for UWB Receiver and Capacitive Sensor Interface
000200483 269__ $$a2014
000200483 260__ $$bEPFL$$c2014$$aLausanne
000200483 336__ $$aTheses
000200483 502__ $$aDr B. Kawkabani (président) ; Dr C. Dehollain (directrice) ; Prof. J.-B. Begueret,  Prof. A. P. Burg,  Prof. W. A. Serdijn (rapporteurs)
000200483 520__ $$aAs CMOS processes continue to scale to smaller dimensions, the increased fT of the devices and smaller parasitic capacitance allow formore power efficient and faster digital circuits to be made. But at the same time, output impedance of transistors has gone down, as have the power supply voltages, and leakage currents have increased. These changes in the technology havemade analog design more difficult.More specifically, the design of a high gain op-amp, a fundamental analog building block, has becomemore difficult in scaled processes. In this work, to improve the performance considering the speed, accuracy and power consumption of the analog-digital interface, both system level optimization and circuit level technique are explored. At first, a generalized graphic model (GGM) is proposed to analyze the resolution of ADC for wireless receiver. This model could show the trade-off between ADC the RF front-end in the power level graph. As a result, the optimization between them becomes practical. Next, two kinds of open loop ADCs are designed and implemented for ultra-wide bandwidth (UWB) receiver and capacitive sensor interface respectively. There is no closed loop stage in the flash ADC, which ensures the fastest conversion speed. An intended spatial filter technique is adopted to attenuate the distortion coming from the interpolation network. The successive approximation (SAR) ADC based switched capacitor sensor interface digitizes the capacitance variation to binary code. A cascade binary weighted DAC is used to reduce the power consumption and area. The noise and distortion performance are optimized throughout the design.
000200483 6531_ $$aData Acquisition
000200483 6531_ $$aAnalog-to-Digital Conversion
000200483 6531_ $$aUWB
000200483 6531_ $$aFlash ADC
000200483 6531_ $$aAveraging
000200483 6531_ $$aSpatial Filtering
000200483 6531_ $$aSAR ADC
000200483 6531_ $$aSwitched Capacitor
000200483 6531_ $$aC2V
000200483 6531_ $$aNoise
000200483 6531_ $$aCapacitive Sensor
000200483 700__ $$0245213$$g197942$$aWang, Shenjie
000200483 720_2 $$aDehollain, Catherine$$edir.$$g107331$$0241196
000200483 8564_ $$uhttps://infoscience.epfl.ch/record/200483/files/EPFL_TH6176.pdf$$zn/a$$s18471303$$yn/a
000200483 909CO $$qDOI2$$qGLOBAL_SET$$pthesis$$pthesis-bn2018$$pDOI$$ooai:infoscience.tind.io:200483
000200483 917Z8 $$x108898
000200483 917Z8 $$x108898
000200483 917Z8 $$x108898
000200483 917Z8 $$x108898
000200483 918__ $$dEDMI$$cIEL$$aSTI
000200483 919__ $$aSCI-STI-CD
000200483 920__ $$b2014$$a2014-8-28
000200483 970__ $$a6176/THESES
000200483 973__ $$sPUBLISHED$$aEPFL
000200483 980__ $$aTHESIS