Performance Optimization and FPGA Implementation of Real-Time Tone Mapping

This brief analyzes the performance of the hardware-based tone mapping operators for compression of high dynamic range images. The bottlenecks of a tone mapping system are determined and a high-performance field programmable gate array (FPGA) implementation of an operator is introduced. The operator utilizes polynomial mapping technique, adaptive to the pixel values; hence preserving high contrast areas. The technique is further optimized for the presented resource-efficient FPGA implementation. We show that the timing optimization does not reduce the image quality, by obtaining high peak signal-to-noise ratio of the resulting images. The timing comparison to the similar implementations shows 2.5 times increase in the achieved throughput, irrespective of the hardware platform.


Published in:
IEEE Transactions on Circuits and Systems Part 2 Express Briefs, 61, 10, 803-807
Year:
2014
Publisher:
Piscataway, Institute of Electrical and Electronics Engineers
ISSN:
1549-7747
Keywords:
Laboratories:




 Record created 2014-07-27, last modified 2018-12-03

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