000199970 001__ 199970
000199970 005__ 20190316235929.0
000199970 037__ $$aPOST_TALK
000199970 245__ $$aLow Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication
000199970 269__ $$a2014
000199970 260__ $$c2014
000199970 336__ $$aPosters
000199970 520__ $$a3D-ICs based on TSV technology provide high bandwidth inter-chip connections. The drawback is that most of the existing TSVs consume a large amount of silicon real estate. We present circuit-level design and analysis of area efficient, low power, high-data-rate 3D serial TSV links. A design space exploration is performed and trade-offs in terms of area, power and performance are presented. Circuit simulations of RC-extracted layouts in 40nm CMOS-technology reveals that 8:1 serialization efficiently balances area consumption and energy efficiency. Using 10μm-diameter TSV technology, an 8Gb/s serial link consumes only 84fJ/bit with 10X area reduction over 8b parallel bus.
000199970 700__ $$0242424$$g188027$$aBeanato, Giulia
000199970 700__ $$0242449$$g176546$$aCevrero, Alessandro
000199970 700__ $$g167918$$aDe Micheli, Giovanni$$0240269
000199970 700__ $$aLeblebici, Yusuf$$g112194$$0240162
000199970 7112_ $$dJune 2-6, 2014$$cSan Francisco, California, USA$$a51st Design Automation Conference (DAC)
000199970 8564_ $$uhttps://infoscience.epfl.ch/record/199970/files/PosterDAC14.pdf$$zn/a$$s4495605$$yn/a
000199970 909C0 $$xU11140$$0252283$$pLSI1
000199970 909CO $$pposter$$ooai:infoscience.tind.io:199970$$qGLOBAL_SET$$pSTI$$pIC
000199970 917Z8 $$x112915
000199970 937__ $$aEPFL-POSTER-199970
000199970 973__ $$aEPFL
000199970 980__ $$aPOSTER