000199970 001__ 199970
000199970 005__ 20180913062546.0
000199970 037__ $$aPOST_TALK
000199970 245__ $$aLow Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication
000199970 269__ $$a2014
000199970 260__ $$c2014
000199970 336__ $$aPosters
000199970 520__ $$a3D-ICs based on TSV technology provide high bandwidth inter-chip connections. The drawback is that most of the existing TSVs consume a large amount of silicon real estate. We present circuit-level design and analysis of area efficient, low power, high-data-rate 3D serial TSV links. A design space exploration is performed and trade-offs in terms of area, power and performance are presented. Circuit simulations of RC-extracted layouts in 40nm CMOS-technology reveals that 8:1 serialization efficiently balances area consumption and energy efficiency. Using 10μm-diameter TSV technology, an 8Gb/s serial link consumes only 84fJ/bit with 10X area reduction over 8b parallel bus.
000199970 700__ $$0242424$$aBeanato, Giulia$$g188027
000199970 700__ $$0242449$$aCevrero, Alessandro$$g176546
000199970 700__ $$0240269$$aDe Micheli, Giovanni$$g167918
000199970 700__ $$0240162$$aLeblebici, Yusuf$$g112194
000199970 7112_ $$a51st Design Automation Conference (DAC)$$cSan Francisco, California, USA$$dJune 2-6, 2014
000199970 8564_ $$s4495605$$uhttps://infoscience.epfl.ch/record/199970/files/PosterDAC14.pdf$$yn/a$$zn/a
000199970 909C0 $$0252283$$pLSI1$$xU11140
000199970 909CO $$ooai:infoscience.tind.io:199970$$pSTI$$pIC$$pposter
000199970 917Z8 $$x112915
000199970 937__ $$aEPFL-POSTER-199970
000199970 973__ $$aEPFL
000199970 980__ $$aPOSTER