Advanced CMOS Circuits for Multi-Gb/s Links and 3D I/O Based on Through Silicon Via Technology
2014
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Details
Title
Advanced CMOS Circuits for Multi-Gb/s Links and 3D I/O Based on Through Silicon Via Technology
Author(s)
Cevrero, Alessandro
Advisor(s)
Date
2014
Publisher
Lausanne, EPFL
Keywords
capactive-DAC; CMOS-postprocessing; chip-multiprocessor (CMP); cross-DFE (XDFE); cross-CTLE (XCTLE); Cu electroplating; continuous-time linear equalizer (CTLE); deep reactive ion etching (DRIE); decision-feedback equalizer (DFE); delayed decision-feedback sequence estimator (DDFSE); Ethernet; far-end-crosstalk (FEXT) cancellation; low-density parity-check (LDPC) decoder; maximum-likelihood-sequence estimator (MLSE); single ended I/O; SOI-CMOS; source-synchronous link; switched-capacitor (SC) DFE; through silicon via (TSV); 3D integration; 60 GHz wireless communication; 10GBASE-T
Language
English
Other identifier(s)
urn: urn:nbn:ch:bel-epfl-thesis6112-1
Record Appears in
Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > LSM - Microelectronic Systems Laboratory
Scientific production and competences > I&C - School of Computer and Communication Sciences > IINFCOM > LAP - Processor Architecture Laboratory
Scientific production and competences > EPFL Theses
Work produced at EPFL
Published
Theses
Scientific production and competences > I&C - School of Computer and Communication Sciences > IINFCOM > LAP - Processor Architecture Laboratory
Scientific production and competences > EPFL Theses
Work produced at EPFL
Published
Theses
Record creation date
2014-05-12