000197688 001__ 197688
000197688 005__ 20190416220314.0
000197688 0247_ $$2doi$$a10.1109/Tcsi.2014.2333675
000197688 022__ $$a1549-8328
000197688 02470 $$2ISI$$a000343003100009
000197688 037__ $$aARTICLE
000197688 245__ $$aConfigurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs
000197688 269__ $$a2014
000197688 260__ $$bInstitute of Electrical and Electronics Engineers$$c2014$$aPiscataway
000197688 300__ $$a11
000197688 336__ $$aJournal Articles
000197688 520__ $$aSilicon nanowire transistors with Schottky-barrier contacts exhibit both n-type and p-type characteristics under different bias conditions. Polarity controllability of silicon nanowire transistors has been further demonstrated by using an additional polarity gate. The device can be configured as n-type or p-type by controlling the polarity gate voltage. This paper extends this approach by using three independent gates and shows its interest to implement dual-threshold-voltage configurable circuits. Polarity and threshold voltage of uncommitted devices are determined by applying different bias patterns to the three gates. Uncommitted logic gates can thus be configured to implement different logic functions, targeting either high-performance or low-leakage applications. Dual-threshold-voltage design is thereby achievable through the use of a wiring scheme on an uncommitted pattern. With the polarity controllability of the three-independent-gate device, a range of logic functions is also obtained by replacing VDD and GND by complementary input signals. Synthesis results of ISCAS’85 and VTR sequential benchmark circuits with these devices show, before place and route, comparable performance and 51% reduction of leakage power consumption compared to 22-nm low-standby-power FinFET technology.
000197688 6531_ $$aambipolar
000197688 6531_ $$asilicon nanowire
000197688 6531_ $$adual-threshold-voltage
000197688 6531_ $$aconfigurable
000197688 700__ $$0245831$$g212096$$aZhang, Jian
000197688 700__ $$0247487$$g214644$$aTang, Xifan
000197688 700__ $$aGaillardon, Pierre-Emmanuel
000197688 700__ $$0240269$$g167918$$aDe Micheli, Giovanni
000197688 773__ $$j61$$tIEEE Transactions on Circuits and Systems Part 1 Regular Papers$$k10$$q2851-2861
000197688 8564_ $$uhttps://infoscience.epfl.ch/record/197688/files/06858094.pdf$$zn/a$$s1528030$$yn/a
000197688 909C0 $$xU11140$$0252283$$pLSI1
000197688 909CO $$particle$$ooai:infoscience.tind.io:197688$$qGLOBAL_SET$$pSTI$$pIC
000197688 917Z8 $$x112915
000197688 917Z8 $$x112915
000197688 937__ $$aEPFL-ARTICLE-197688
000197688 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000197688 980__ $$aARTICLE