3-D integration is a promising prospect for implementing high performance multifunctional systems-on- chip. Through Silicon Vias (TSVs) are the enablers for achieving high bandwidth paths in inter-plane communications. TSVs also provide higher vertical link density and facilitate the heat flow in the 3-D circuits as compared to other potential schemes such as inductive links. However, reliability issues and crosstalk problems among adjacent TSVs decrease the yield and performance of TSV based circuits. Reducing the number of TSVs employed for inter-plane signal transferring can alleviate these problems. This paper proposes to exploit serialization to reduce the number of TSVs in a 3D circuit and presents a comparison between different aspects of TSV-based 3-D circuits such as area, power, crosstalk and yield in parallel and serial vertical links.