Investigation of Tunnel Field-Effect Transistors as a Capacitor-less Memory Cell

In this work we report experimental results on the use of Tunnel Field-Effect Transistors (TFET) as capacitorless Dynamic Random Access Memory (DRAM) cells, implemented as a double-gate (DG) Fully-Depleted Silicon-On-Insulator (FD-SOI) devices. The devices have an asymmetric design, with a partial overlap of the top gate (LG) with a total overlap of the back gate over the channel region (LG+LIN). A potential well is created by biasing the back gate (VBG) in accumulation while the front gate (VFG) is in inversion. Holes from the p+ source are injected by the forward-biased p+i junction and stored in the electrically induced potential well.


Published in:
Applied Physics Letters, 104, 9, 092108
Year:
2014
Publisher:
Melville, American Institute of Physics
ISSN:
0003-6951
Keywords:
Laboratories:




 Record created 2014-02-24, last modified 2018-03-17

External link:
Download fulltext
URL
Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)