Evaluation of the SPUR Lisp Architecture

The SPUR microprocessor has a 40-bit tagged architecture designed to improve its performance for Lisp programs. Although SPUR includes just a small set of enhancements to the Berkeley RISC-II architecture, simulation results show that with a 150-ns cycle time SPUR will run Common Lisp programs at least as fast as a Symbolies 3600 or a DEC VAX 8600. This paper explains SPUR's instruction set architecture and provides measurements of how certain components of the architecture perform.


Published in:
13th International Symposium on Computer Architecture, 444-452
Year:
1986
Publisher:
ACM
Laboratories:




 Record created 2013-12-23, last modified 2018-01-28

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