000191183 001__ 191183
000191183 005__ 20190416220311.0
000191183 0247_ $$2doi$$a10.7873/DATE.2014.248
000191183 037__ $$aCONF
000191183 245__ $$aAdvanced System on a Chip Design Based on Controllable-Polarity FETs (invited paper)
000191183 269__ $$a2014
000191183 260__ $$bIEEE$$c2014
000191183 336__ $$aConference Papers
000191183 520__ $$aField-Effect Transistors (FETs) with on-line controllable-polarity are promising candidates to support next generation System-on-Chip (SoC). Thanks to their enhanced functionality, controllable-polarity FETs enable a superior design of critical components in a SoC, such as processing units and memories, while also providing native solutions to control power consumption. In this paper, we present the efficient design of a SoC core with controllable-polarity FET. Processing units are speeded-up at the datapath level, as arithmetic operations require fewer physical resources than in standard CMOS. Power consumption is decreased via embedded power-gating techniques and tunable high-performance/low-power devices operation. Memory cells are made smaller by merging the access interface with the storage circuitry. We foresee the advantages deriving from these techniques, by evaluating their impact on the design of SoC for a contemporary telecommunication application. Using a 22-nm vertically-stacked silicon nanowire technology, a coarse-grain evaluation at the block level estimates a delay and power reduction of 20% and 19% respectively, at a cost of a moderate area overhead of 15%, with respect to a state-of-art FinFET technology.
000191183 6531_ $$afunctionality-enhanced devices
000191183 6531_ $$asystem-on-chip
000191183 6531_ $$adatapath
000191183 6531_ $$alow-power techniques
000191183 700__ $$aGaillardon, Pierre-Emmanuel
000191183 700__ $$aAmaru, Luca
000191183 700__ $$0245831$$g212096$$aZhang, Jian
000191183 700__ $$aDe Micheli, Giovanni$$g167918$$0240269
000191183 7112_ $$dMarch 10-14, 2014$$cDresden, Germany$$aDesign, Automation and Test in Europe Conference (DATE)
000191183 773__ $$tDesign, Automation and Test in Europe Conference and Exhibition (DATE), 2014
000191183 8564_ $$uhttps://infoscience.epfl.ch/record/191183/files/PEG_DATE14_v08.pdf$$zn/a$$s705465$$yn/a
000191183 909C0 $$xU11140$$0252283$$pLSI1
000191183 909CO $$pIC$$ooai:infoscience.tind.io:191183$$qGLOBAL_SET$$pconf$$pSTI
000191183 917Z8 $$x112915
000191183 917Z8 $$x112915
000191183 917Z8 $$x112915
000191183 917Z8 $$x112915
000191183 937__ $$aEPFL-CONF-191183
000191183 973__ $$rNON-REVIEWED$$sPUBLISHED$$aEPFL
000191183 980__ $$aCONF