000190740 001__ 190740
000190740 005__ 20190331192645.0
000190740 022__ $$a0018-9200
000190740 02470 $$2ISI$$a000327548900011
000190740 037__ $$aARTICLE
000190740 245__ $$aA 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS
000190740 269__ $$a2013
000190740 260__ $$bInstitute of Electrical and Electronics Engineers$$c2013
000190740 336__ $$aJournal Articles
000190740 520__ $$aAn 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step. High-speed operation is achieved by converting each sample with two alternate comparators clocked asynchronously and a redundant capacitive DAC with constant common mode to improve the accuracy of the comparator. A low-power, clocked capacitive reference buffer is used, and fractional reference voltages are provided to reduce the number of unit capacitors in the capacitive DAC (CDAC). The ADC stacks the CDAC with the reference capacitor to reduce the area and enhance the settling speed. Background calibration of comparator offset is implemented. The ADC consumes 3.1 mW from a 1 V supply and occupies 0.0015 mm².
000190740 6531_ $$aSAR ADC
000190740 6531_ $$aSOI
000190740 6531_ $$aCMOS
000190740 700__ $$0242446$$aKull, Lukas$$g197929
000190740 700__ $$aToifl, T.
000190740 700__ $$aSchmatz, M.
000190740 700__ $$aFrancese, P. A.
000190740 700__ $$aMenolfi, C.
000190740 700__ $$aBraendli, M.
000190740 700__ $$aKossel, M.
000190740 700__ $$aMorf, T.
000190740 700__ $$aMeyer Andersen, T.
000190740 700__ $$0240162$$aLeblebici, Y.$$g112194
000190740 773__ $$j48$$k12$$q3049-3058$$tIEEE Journal of Solid State Circuits
000190740 909C0 $$0252051$$pLSM$$xU10325
000190740 909CO $$ooai:infoscience.tind.io:190740$$pSTI$$particle
000190740 917Z8 $$x112194
000190740 937__ $$aEPFL-ARTICLE-190740
000190740 973__ $$aEPFL$$rREVIEWED$$sPUBLISHED
000190740 980__ $$aARTICLE