A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS
Kull, Lukas; Toifl, T.; Schmatz, M.; Francese, P. A.; Menolfi, C.; Braendli, M.; Kossel, M.; Morf, T.; Meyer Anderson, T.; Leblebici, Yusuf
2014

Abstract

A 90GS/s 8b low-power ADC is presented achieving 33.0-36.0dB SNDR and a FoM of 203fJ/conversion-step. High conversion speed of up to 100GS/s and high input bandwidth of 22GHz is achieved by using a 1:64 interleaver with integrated sampling. Single NMOS transistors followed by 1:4 demux stages are used to sample the signal. Skew and gain adjustment is implemented on-chip. The ADC consumes 667mW at 90GS/s and 845mW at 100GS/s and can be operated from a single supply voltage. It is implemented in 32nm SOI CMOS and occupies 0.45mm2.

Details

Title A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS
Author(s) Kull, Lukas ; Toifl, T. ; Schmatz, M. ; Francese, P. A. ; Menolfi, C. ; Braendli, M. ; Kossel, M. ; Morf, T. ; Meyer Anderson, T. ; Leblebici, Yusuf
Published in Proceedings of the 2014 International Solid-State Circuits Conference (ISSCC)
Conference 2014 International Solid-State Circuits Conference (ISSCC), San Francisco, California, February 9-13, 2014
Date 2014
Keywords
Laboratories LSM
Record Appears in Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > LSM - Microelectronic Systems Laboratory
Peer-reviewed publications
Conference Papers
Work produced at EPFL
Accepted
Record creation date 2013-11-26

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