Hardware-efficient steering matrix computation architecture for MIMO communication systems
Beamforming (BF) improves the error rate performance of multiple-input multiple-output (MIMO) wireless communication systems by spatial separation of the transmitted data streams. Spatial separation is achieved by multiplication of the transmit vector by a steering matrix, which is obtained through the singular value decomposition (SVD) of the channel matrix. In this paper, we describe a hardware-efficient VLSI architecture for steering matrix computation using a hardware- optimized SVD algorithm. Our architecture contains a high-speed Givens rotation unit which achieves high processing throughput at low area. The resulting VLSI implementation requires 3.3 mus per steering matrix computation at an expense of 41.3 kGEs and shows a 3.5-fold hardware-efficiency gain compared to a reference SVD implementation.
Keywords: MIMO communication ; VLSI ; digital arithmetic ; singular value decomposition ; VLSI architecture ; beamforming ; data stream spatial separation ; hardware-efficient steering matrix computation architecture ; high speed Givens rotation ; Array signal processing ; Matrix decomposition
Record created on 2013-10-29, modified on 2016-08-09