A Common Core Model for Junctionless Nanowires and Symmetric Double Gate FETs

In this brief, we evidence the link between planar and cylindrical junctionless FETs from the electrostatics point of view. In particular, we show that an approximate solution of the Poisson-Boltzmann equation for junctionless nanowires can be mapped on the planar double gate topology generating only negligible mismatch, meaning that both devices can simply share the same model as far as long channels are considered. These preliminary results are a first step towards a unification of compact models for junction less FETs.


Published in:
IEEE Transactions on Electron Devices, 60, 12, 4277-4280
Year:
2013
Publisher:
Piscataway, Institute of Electrical and Electronics Engineers
ISSN:
0018-9383
Keywords:
Laboratories:




 Record created 2013-10-18, last modified 2018-09-13


Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)