Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors

This brief presents a novel power-gating technique for differential cascade voltage switch logic (DCVSL) based on double-gate (DG) controllable-polarity field-effect transistors (FETs). DG controllable-polarity FETs, commonly referred to as ambipolar transistors, are devices whose polarity is online reconfigurable by changing the second gate bias. In this brief, we exploit the online control of ambipolar device polarity to achieve intrinsically power-gated DCVSL circuits bypassing the use of series sleep transistors. We perform circuit-level simulations and comparisons at 22-nm technology node, considering silicon nanowire-based DG controllable-polarity FETs. Experimental results show that ambipolar DCVSL circuits power gated by the proposed technique have on average $6times$ smaller standby power with only $1.1times$ timing penalty with respect to their non-power-gated versions. As compared with unipolar FinFET-based realizations, our proposal is capable to reduce up to $1.9times$ the standby power consumption of a low-standby-power process and, at the same time, increase up to 10% the performance of a high-performance process.

Published in:
IEEE Transcations on Circuits and Systems II: Express Briefs, 60, 10, 672-676
Piscataway, Ieee-Inst Electrical Electronics Engineers Inc

 Record created 2013-09-24, last modified 2019-03-16

Download fulltext

Rate this document:

Rate this document:
(Not yet reviewed)