Conference paper

Heavily Doped Junctionless Vertical Slit FETs with Slit Width Below 20 nm

This paper reports an alternative simple fabrication process for twin gate junctionless Vertical Slit Field Effect Transistors. N-type devices have been successfully manufactured on SOI substrates with a doping density 5×1018 atoms/cm3. The devices demonstrate up to six decades of Ion/Ioff ratio and a sub- threshold swing of 90 mV/decade relative to a slit width of approximately 10 nm.


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