Design Space of Twin Gate Junctionless Vertical Slit Field Effect Transistors

In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space involving the intrinsic off-current, the sub-threshold swing, and the drain induced barrier lowering is investigated with respect to the technological parameters. This work could serve as a guideline for technology optimization and design of JL VeSFETs.


Presented at:
Mixed Design of Integrated Circuits & Systems, 2013 MIXDES'13. MIXDES-20th International Conference, Gdynia, Poland, June 20-22, 2013
Year:
2013
Keywords:
Laboratories:




 Record created 2013-08-07, last modified 2018-01-28


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