Towards fabrication of Vertical Slit Field Effect Transistor (VeSFET) as new device for nano-scale CMOS technology
2011
Abstract
This paper proposes a CMOS based process for Vertical Slit Field Effect Transistors. The central part of the device, namely, the vertical slit, is defined by using electron beam lithography and silicon dry etching. In order to verify the validity and the reproducibility of the process, devices having the slit width ranging from 16 nm to 400 nm were fabricated, with slit conductance in the range 0.6 to 3 milliSiemens, in agreement with the expected values. © 2011 IEEE.
Details
Title
Towards fabrication of Vertical Slit Field Effect Transistor (VeSFET) as new device for nano-scale CMOS technology
Author(s)
Barbut, Lucian ; Bouvet, Didier ; Sallese, Jean-Michel
Published in
CAS 2011 Proceedings (2011 International Semiconductor Conference)
Pages
325-328
Conference
2011 International Semiconductor Conference (CAS 2011), Sinaia, Romania, 17-19 October 2011
Date
2011
Publisher
IEEE
Record Appears in
Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > EDLAB - Group of Electron Device Modeling and Technology
Scientific production and competences > STI - School of Engineering > CMI - Center of MicroNanoTechnology
Peer-reviewed publications
Conference Papers
Work produced at EPFL
Published
Scientific production and competences > STI - School of Engineering > CMI - Center of MicroNanoTechnology
Peer-reviewed publications
Conference Papers
Work produced at EPFL
Published
Record creation date
2013-08-07