With technology scaling reaching the fundamental limits of Si-CMOS in the near future, the semiconductor industry is in quest for innovation from various disciplines of integrated circuit (IC) design. At a fundamental level, technology forms the main driver for innovation, where emerging nanotechnologies based on new transistor material are being investigated. For instance technologies based on nanowires and nanotubes are promising contenders for Si-CMOS due to their high energy efficiency and improved channel properties. The second driver for innovation in IC design is three dimensional (3D) integration. 3D technologies are proven to be cost effective and are being adopted by all the leading fabs. One key driver for the future of IC design is the shift in the design paradigm. Computing paradigms based on new capabilities offered by nanodevices open up new venues for innovation in the field of IC design. This thesis aims at bridging paths between technology and design for exploring new nanotechnologies. This thesis is organized across three different nanotechnologies with an aim to provide novel circuits, architectures and design methodologies in order to leverage the new capabilities offered by these technologies. The considered nanotechnologies are: 3D monolithic integration (3DMI), Silicon nanowire FET (SiNWFET), and Carbon nanotube FET (CNFET). The novelty and contributions of this thesis consists of proposing design methodologies and developing computer aided design (CAD) tools for these nanotechnologies by taking into account the technology constraints. This thesis has an interdisciplinary vision involving process, design and CAD for emerging nanotechnologies. In the first part of the thesis, a physi- cal design tool (CELONCEL) is developed for ultra fine-grain 3DMI circuits, whereby the main aim is to evaluate the performance of 3DMI technology for ASIC design. The second part of the thesis deals with layout technique for double-gate silicon nanowire FET (DG-SiNWFET) when applied to ambipo- lar logic circuits. Novel layout synthesis algorithm is proposed for complex Boolean functions with embedded XOR/XNOR functionality. In the final part of the thesis, robust design techniques for CNFET circuits are presented, whereby the goal is to improve the yield while considering CNT imperfections. Two layout techniques are proposed which take into account mispositioned- immune CNTs and CNT-correlation. For the first time CNFET circuits are benchmarked at a system-level with their respective CMOS counterparts.