Efficient Arithmetic Logic Gates Using Double-Gate Silicon Nanowire FETs, invited paper

Silicon NanoWire (SiNW) based Field Effect Tran- sistors (FETs) are promising candidates to extend Moore’s law in the coming years. Recently, Double-Gate (DG) SiNWFETs have been demonstrated to allow on-line configurability of n -type and p -type device polarity through the second gate. Such feature enables novel compact realizations for XOR- and MAJ-based logic gates that are intensively used in arithmetic applications. In this paper, we present a complete design framework of DG- SiNWFETs technology for arithmetic logic. We characterize and validate compact arithmetic logic gates (XOR, MAJ, FA) using circuit level simulations. SiNW-based controllable polarity transistors at 22-nm technology node, first characterized at the physical level with Synopsys Sentaurus, enable a full-adder implementation about 3.8x faster than its CMOS FinFET 22-nm counterpart, according to HSPICE circuit simulations. Then, we study the application of these arithmetic gates in the automated synthesis of datapath circuits which are dominated by arithmetic operations. Experimental results show that datapath circuits synthesized in DG-SiNWFETs 22-nm technology are about 1.5x faster than in CMOS FinFET 22-nm technology while having practically the same area occupation.

Published in:
Proceedings of the 11th IEEE International NEWCAS Conference
Presented at:
11th IEEE International NEWCAS Conference, Paris, France, June 16-19, 2013

 Record created 2013-06-13, last modified 2019-03-16

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