A Parallelized Layered QC-LDPC Decoder for IEEE 802.11ad

We present a doubly parallelized layered quasi-cyclic low density parity-check decoder for the emerging IEEE 802.11ad multigigabit wireless standard. The decoding algorithm is equivalent to a nonparallelized layered decoder and, thus, retains its favorable convergence characteristics, which are known to be superior to those of flooding schedule based decoders. The proposed architecture was synthesized using a TSMC 40 nm CMOS technology, resulting in a cell area of 0.18 mm2 and a clock frequency of 850 MHz. At this clock frequency, the decoder achieves a coded throughput of 3.12 Gbps, thus meeting the throughput requirements when using both the mandatory BPSK modulation and the optional QPSK modulation.


Published in:
2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)
Presented at:
11th IEEE International NEWCAS Conference, Paris, France, June 16-19, 2013
Year:
2013
Publisher:
Piscataway, IEEE
Laboratories:




 Record created 2013-06-02, last modified 2018-03-18

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