A Scalable and Adaptive Technique for Compensating Process Variations and Controlling Leakage and Delay in the FPGA

A new circuit style is proposed to tune the delay, subthreshold leakage (ISUB), and gate leakage (IG) of high fan-in multiplexer circuits, such as the FPGA Look-Up Table (LUT) and Switch-Box (SB), without increasing the Gate Induced Drain Leakage (GIDL) current or causing any reliability problems. In the proposed Adaptive Vgs (AVGS) style, Regular Threshold Voltage (RVT) transistors are replaced with the Low-VT (LVT) ones, but during the active-mode, new transistors have Vgs = - ΔV in the OFF and Vgs = VDD - ΔV in the ON conditions where ΔV is a new adjustable supply rail. AVGS can be a scalable replacement of the Adaptive Body Biasing (ABB) and Adaptive Supply Voltage (ASV) techniques in emerging manufacturing technologies that have very small body effect and cannot tolerate voltages higher than the nominal supply voltage (VDD) due to the reliability issues. Proposed technique is verified on silicon in the 90 nm technology and remarkable results are observed. AVGS can also be utilized to customize the FPGA delay-leakage trade-off. Area, leakage, dynamic power, and performance overheads are small.

Published in:
Journal of Low Power Electronics, 9, 1, 1-8
American Scientific Publishers

 Record created 2013-06-01, last modified 2018-03-17

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